At advanced process nodes, conventional planar transistor architectures suffer from a number of problems such as excessive leakage. As a result, three-dimensional architectures such as a fin field effect transistor (finFET) process are conventionally used at these advanced nodes. The “fin” in a finFET device comprises a three-dimensional bar on the semiconductor substrate. The fin thus has a lower surface adjoining the substrate surface and three remaining surfaces that project above the substrate surface. The gate is then deposited over the fin such that the gate is directly adjacent these three remaining surfaces of the fin. In contrast, the gate is directly adjacent only one surface of the channel in a conventional planar architecture. The channel can thus be cut off more effectively in a finFET device, which reduces leakage currents and makes the advanced process nodes tenable.
Although finFETs are thus advantageous, the gate cannot directly control the fin surface that adjoins the substrate surface. To provide even better gate control, gate-all-around architectures have been developed in which the fin is transformed into one or more nanowires suspended from the substrate surface. Gate-all-around devices may thus also be denoted as nanowire devices or transistors. To start the formation of a nanowire transistor, a well implant is formed in the semiconductor substrate. Then, the foundry deposits alternating layers of Si and SiGe over the well implant. These alternating layers are then etched to form a fin. The foundry then deposits shallow trench isolation oxide fill around the fins followed by a dummy gate formation. After the dummy gate formation, the foundry performs an extension implant, spacer deposition, source/drain epitaxial (epi) growth, junction implant, inter-layer dielectric (ILD0) fill, whereupon the dummy gate is removed. With the dummy gate removed, the nanowires may then be formed by either selectively etching the Si layers in the fin or selectively etching the SiGe layers. If SiGe layers are removed, the resulting nanowires are silicon. Conversely, if the silicon layers are selectively etched, the nanowires are SiGe. The gate structure may then be deposited around the nanowires.
Despite the resulting nanowire device having better gate control than a comparable finFET device, the selective etching of silicon germanium (or silicon) layers through the window between the spacers prior to the gate deposition produces an undercut beneath the spacers. Given the undercutting of the SiGe or Si layers, the subsequent gate-to-source and gate-to-drain parasitic capacitance is relatively high. In addition, the bottom parasitic channel in the well implant below the gate is not controlled well since there is no gate-all-around contact for this bottom parasitic channel. It will thus conduct an undesirable leakage current. In addition, there is an undesirable parasitic capacitance between the gate and the bottom parasitic channel.
There is thus a need in the art for improved nanowire device architectures with reduced parasitic capacitance and reduced parasitic channel effects.